What is AXI Lite? - YouTube
Building a custom yet functional AXI-lite slave
AXI Bus
3. AXI4-Lite Cross-bar Interconnect — Interconnect IPs 1.1.6 documentation
Using a formal property file to verify an AXI-lite peripheral
Deploy Model with AXI-Stream Interface in Zynq Workflow - MATLAB & Simulink - MathWorks France
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO – Mehmet Burak Aykenar
AXI4-Lite write timing simulation Figure 7. AXI4-Lite read timing... | Download Scientific Diagram
Building a custom yet functional AXI-lite slave
AXI-Full and AXI-Lite Interfaces - Logic Fruit Technologies
AXI Basics 6 - Introduction to AXI4-Lite in Vitis HLS
Advanced eXtensible Interface - Wikipedia
AXI-lite interface hardware behaviour. | Download Scientific Diagram
Understanding the AMBA AXI4 Spec - Circuit Cellar
Welcome to Real Digital
How to send data from AXI-LITE port to PL and receive data from AXI DMA - Support - PYNQ
AXI4-Lite Interface - 4.3 English
Creating example project with AXI4 Lite peripheral in Xilinx Vivado - ift
AMBA AXI4-Lite Interconnect Verification IP
Buidilng an AXI-Lite slave the easy way
If someone is looking for how to design AXI Lite system, then here's the axi lite master specification. I wrote the AXI Lite master part in verilog. I have used AXI Stream
3. AXI4-Lite Cross-bar Interconnect — Interconnect IPs 1.1.6 documentation
Figure 7 from A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC | Semantic Scholar
